Semiconductor device

ABSTRACT

A semiconductor device having a semiconductor die, a redistribution layer (RDL), and an encapsulant. The RDL layer can be formed on a first surface of the semiconductor die. The encapsulant can enclose a second surface and side surfaces of the semiconductor die. The encapsulant can enclose side portions of the RDL.

TECHNICAL FIELD

The present disclosure relates generally to semiconductor devices andmethods.

BACKGROUND

An integrated circuit (IC) can be a set of electronic circuits on onesmall flat piece (“chip”) of semiconductor material (e.g., silicon). TheIC can include a large number of tiny transistors integrated into asmall chip resulting in circuits that can be smaller and faster thanthose constructed of discrete electronic components. The IC can bepackaged at a wafer level, in contrast to a process of assemblingindividual units in packages after dicing them from a wafer. In itsfinal form, the IC can be a die with an array pattern of bumps or solderballs attached at an input/output (I/O) pitch that is compatible withcircuit board assembly processes.

A semiconductor die assembly may include a plurality of memory die, andthe substrate associated with the plurality of memory die may be anorganic or inorganic substrate. Semiconductor die assemblies can be usedin a variety of electronic applications, such as personal computers,cell phones, digital cameras, and other semiconductor devices. Thesemiconductor device can include at least one semiconductor die coupledto a substrate through a plurality of conductive structures (e.g.,metals, wires, conductive lines, solderbumps, etc.). The plurality ofconductive structures can be within a redistribution layer that helpsconnect the semiconductor die to the substrate. The redistribution layercan be exposed to conditions from the outside of the semiconductordevice which can lead to interfacial delamination, crack-inducedmechanical stress, moisture impact, among other issues, during anassembly process and/or during use. The semiconductor die can includefunctional features, such as memory cells, processor circuits, imagercomponents, and interconnecting circuitry.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A is an example of a semiconductor device in accordance with anumber of embodiments of the present disclosure.

FIG. 1B is an example of a portion of a semiconductor device inaccordance with a number of embodiments of the present disclosure.

FIG. 2A is an example of a semiconductor device in accordance with anumber of embodiments of the present disclosure.

FIG. 2B is an example of a portion of a semiconductor device inaccordance with a number of embodiments of the present disclosure.

FIGS. 3A-3H are an example of a method of forming a semiconductor devicein accordance with a number of embodiments of the present disclosure.

FIGS. 4A-4H are an example of a method of forming a semiconductor devicein accordance with a number of embodiments of the present disclosure.

DETAILED DESCRIPTION

A semiconductor device can include a semiconductor die, a redistributionlayer (RDL), and an encapsulant. The RDL layer can be formed on andenclosing a first surface of the semiconductor die. The encapsulant canenclose a second surface and side surfaces of the semiconductor die. Theencapsulant can enclose side portions of the RDL.

A process for forming a semiconductor device can result in a dieattached to a redistribution layer (RDL). In at least one embodiment,the RDL can be a built-up layer that can be fabricated either directlyon a semiconductor die or built on a carrier. The RDL can then betransferred to the die rather than using a pre-formed substrate. The diecan be encased in an encapsulant (e.g., an organic material layer, anepoxy mold compound (EMC), etc.) that surrounds the die. A number ofinterconnect structures (e.g., an interconnect structure, a copperpillar bump, a gold bump, etc.) and/or additional connective componentscan be coupled to the RDL and utilized to electrically connect thesemiconductor device to a number of other semiconductor devices and/orother components of a semiconductor device. The interconnect structurescan be used to connect a circuit on a die to a pin on a packaged chip.The interconnect structure can be an electroplated structure. Forexample, a coating can be formed using an electrolytic deposition withcopper, nickel, tin-silver, silver, old, or another metal, includingalloys of the listed metals, to form an interconnect structure and/or apillar bump.

In some previous approaches, an edge of the RDL can be exposed (e.g.,not encased within the encapsulant) to conditions from the outside ofthe semiconductor device which can lead to interfacial delamination,crack-induced mechanical stress, and moisture impact, among otherissues, during an assembly process and/or during use. As describedfurther below, in at least one embodiment, the edge of the RDL can beencased within an encapsulant (e.g., an organic material layer, an EMC)layer. By encasing the edge of the RDL layer within the encapsulant(e.g., an organic material layer, an EMC layer), the RDL can beprotected from various adverse conditions during the forming processand/or during use.

In at least one embodiment, encapsulants can be formed between a numberof interconnect structures (e.g., solderballs) coupled to the RDL layer.For example, an encapsulant between a first interconnect structure and asecond interconnect structure can be formed along at least a portion ofthe interconnect structure of each of the first interconnect structureand the second interconnect structure and in the space between themalong the RDL. The encapsulant between the interconnect structures canprotect a joint of the interconnect structure from failure (e.g., duringtesting of the semiconductor device).

In some previous approaches, during a fan-out wafer-level packagingprocess (FOWLP), an interconnect structure (e.g., a solder ball)attached to the RDL can be coupled directly to the printed circuit board(PCB). This can cause thermo-mechanical stress generated during a boardlevel test. Due to a stiffness difference between the package and thePCB, a joint failure can occur during a drop test, and a solder jointfailure can occur due to a coefficient of thermal expansion (CTE)difference between the package and the PCB. In at least one embodimentdescribed below, by filling the space between the interconnectstructures with the encapsulant, the affect of the CTE difference can beminimized and reduce the thermos-mechanical stress.

A semiconductor device can include a number of articles of manufacture,including, for example, integrated circuit (IC) dies, imager dies,sensor dies, and/or dies having other semiconductor features. While anumber of examples of semiconductor devices are illustrated in FIGS.1A-4H, examples are not so limited. Components and/or semiconductorfeatures can be altered and/or modified in a number of ways.

In the following detailed description of the present disclosure,reference is made to the accompanying drawings that form a part hereof,and in which is shown by way of illustration how one or more embodimentsof the disclosure may be practiced. These embodiments are described insufficient detail to enable those of ordinary skill in the art topractice the embodiments of this disclosure, and it is to be understoodthat other embodiments may be utilized and that process, electrical,and/or structural changes may be made without departing from the scopeof the present disclosure.

The figures herein follow a numbering convention in which the firstdigit or digits correspond to the drawing figure number and theremaining digits identify an element or component in the drawing.Similar elements or components between different figures may beidentified by the use of similar digits. For example, 114 may referenceelement “14” in FIG. 1A, and a similar element may be referenced as 214in FIG. 2A. Also, as used herein, “a number of” a particular elementand/or feature can refer to one or more of such elements and/orfeatures.

FIG. 1A is an example of a semiconductor device 101 in accordance with anumber of embodiments of the present disclosure. Semiconductor device101 can include a memory chip 110. The memory chip 110 can be, forexample, an integrated circuit including a set of electronic circuits ona single, flat piece of semiconductor material. The semiconductormaterial can be silicon, glass, or other materials.

The semiconductor device 101 can include a redistribution layer 112 thatis a dielectric. A redistribution layer (RDL) 112 refers to an extrametal layer on the memory chip 110 that makes input/output contacts withadditional semiconductor devices (such as an integrated circuitry inadditional locations). The RDL 112 can be an extra layer of wiring onthe memory chip 110 that enables the memory chip 110 to bond out fromdifferent locations on the memory chip 110, making chip-to-chip bondingeasier. Wiring 118 of the RDL 112 can be electrically coupled to anadditional electrical contact (such as interconnect structure 120-5, asillustrated).

The semiconductor device 101 can include an encapsulant (e.g., anorganic material layer, an epoxy mold compound (EMC)) 114 that encases(e.g., surrounds, covers, etc.) the memory chip 110. A first sideportion 116-1 of the encapsulant 114 can encase a first edge of the RDL112 and a second side portion 116-2 of the encapsulant 114 can encase asecond edge of the RDL 112. The encapsulant 114 can be used toencapsulate portions of semiconductor device 101 due to properties ofthe encapsulant 114 that includes high mechanical strength and highproductivity. The encapsulant 114 are solid epoxy polymers that areheated to a liquid and can then be injected over a circuit forprotection of the circuit. By covering the RDL 112 with the first sideportion 116-1 and the second side portion 116-2, the edge of the RDL 112is protected by these properties and can avoid interfacial delamination,cracking induced by moisture, and decrease effects of thermo-mechanicalstress on the edge of the RDL 112. The encapsulant 114 encasing the edgeof the RDL 112 prevents moisture absorption through a sidewall of theRDL 112.

The memory hip 110 can be electrically coupled to a number ofinterconnect structures (such as solderballs) through the RDL 112. Asillustrated, the memory chip 110 is electrically coupled to interconnectstructures 120-1, 120-2, 120-3, 120-4, 120-5, as is illustrated bywiring 118 electrically coupling the memory chip 110 to interconnectstructures 120-5.

FIG. 1B is an example of a portion of a semiconductor device 101 inaccordance with a number of embodiments of the present disclosure. FIG.1B is an example of a bottom view of a memory chip, such as memory chip110 illustrated in FIG. 1A. While five (5) interconnect structures(e.g., solderballs) are illustrated in FIG. 1A, shown as interconnectstructures 120-1 through 120-5, a greater number of interconnectstructures are illustrated in FIG. 1B, a first of which is labeled asinterconnect structures 120 for ease of illustration. The semiconductordevice 101 includes a redistribution layer 112 and an encapsulant (e.g.,EMC) 114. As illustrated from a bottom view in FIG. 1B, the encapsulant114 extends beyond an edge of the RDL 112 to provide protection to theedge of the RDL 112.

FIG. 2A is an example of a semiconductor device 202 in accordance with anumber of embodiments of the present disclosure. The semiconductordevice 202 includes a semiconductor die 210 and a redistribution layer(RDL) 212 that are enclosed by an encapsulant (e.g., an organic materiallayer, an epoxy mold compound (EMC)) 214. A redistribution layer (RDL)212 refers to an extra metal layer on the memory chip 210 that makesinput/output contacts with additional semiconductor devices (such as anintegrated circuitry in additional locations). The RDL 212 can be anextra layer of wiring on the memory chip 210 that enables the memorychip 210 to bond out from different locations on the memory chip 210,making chip-to-chip bonding easier. The RDL 114 can be coupled to anumber of interconnect structures (e.g., solderballs) 210-1, 210-2,210-3, 210-4, 210-5, 210-6, 210-7 (referred to herein as interconnectstructures 210) that coupled the semiconductor die 210 to a printedcircuit board (PCB) 222 through the RDL 214 and the interconnectstructures 220.

The encapsulant 214 encloses the semiconductor die 210, the RDL 212 andin between the interconnect structures 220. In this way, the two edgesof the RDL 212 are enclosed to protect the RDL 212 fromthermos-mechanical stress and interfacial delamination/cracking inducedby moisture. The portions between the interconnect structures 220 on theunderside of the RDL 212 is enclosed by the encapsulant 214 and protectsa side of the RDL 212 facing the PCB 222 and covers the solder jointwhich improves the board level reliability (BLR) statistics. Theencapsulant 214 encloses the side of the RDL 212 facing the PCB 222instead of an underfill (UF) material. Warpage of the RDL 212 isdecreased due to the encapsulant 214 covering the side of the RDL 212facing the PCB 222. A portion 211 of the semiconductor device 202 isexpanded in FIG. 2B for illustrative purposes.

FIG. 2B is an example of a portion 211 of a semiconductor device inaccordance with a number of embodiments of the present disclosure. Theportion 211 of the semiconductor device includes a semiconductor chip210 enclosed by an encapsulant (e.g., an organic material layer, EMC)214. The semiconductor chip 210 is coupled to a redistribution layer(RDL) 212 that is enclosed by an encapsulant 214 on its side. Theencapsulant 214 wraps around the side of the RDL 212 and encloses anunderside of the RDL 212 until the encapsulant 214 meets up with aninterconnect structure 220-7. The encapsulant 214 is betweeninterconnect structures 220-6 and 220-7 on an underside of the RDL 212.In this way, the encapsulant 214 protects the side and underside of theRDL 212 and structurally supports the interconnect structures 220-6,220-7 and holds them in place.

FIGS. 3A-3H are an example of a method of forming a semiconductor devicein accordance with a number of embodiments of the present disclosure.FIG. 3A is an example of an initial step of the method of forming thesemiconductor device which can include making a semiconductor die 210for coupling to a redistribution layer later in the method. FIG. 3B isan example of a subsequent step that can include forming aredistribution layer 312 on a carrier substrate 326. The carriersubstrate 326 can include a glass carrier, a silicon carrier, amongother materials.

FIG. 3C is an example of a subsequent step of the method of forming thesemiconductor device that can include forming an encapsulant (e.g., anorganic material layer, an EMC layer) 314 over the RDL 312 such that theencapsulant 314 encloses a first side (illustrated as the top of the RDL312) of the RDL 312 and side portions 315-1 and 315-2 of the RDL 314. Asillustrated in FIG. 3C, the edge of the RDL 312 can be encased withinthe encapsulant 314. By encasing the edge of the RDL 312 within theencapsulant 314, the RDL 312 can be protected from interfacialdelamination, crack-induced mechanical stress, and moisture impact. Theinterfacial delamination, crack-induced mechanical stress, and/ormoisture impact can occur along the edges of the RDL 312 in the absenceof the encapsulant 314 at the edges 315-1, 315-2 during an assemblyprocess and/or during use.

FIG. 3D is an example of a subsequent step of the method of forming thesemiconductor device that can include removing portions of theencapsulant 314 from a side of the RDL 312. The removal of the portionscan be performed by selective etching with a laser. The removal of theportions can create locations along the RDL 312 that can be used toinsert additional semiconductor components, such as interconnectstructures. The RDL 312, as illustrated, is attached to a carriersubstrate 326. FIG. 3E is an example of a subsequent step of the methodof forming the semiconductor device that can include removing a carriersubstrate (such as carrier substrate 326 in FIG. 3D). FIG. 3Eillustrates the RDL 312 and the encapsulant 314 rotated 180 degrees sothat the removed portions of the encapsulant 314 are facing downward, asillustrated.

FIG. 3F is an example of a subsequent step of the method of forming thesemiconductor device that can include coupling a semiconductor die 310(such as semiconductor die 310 described in FIG. 3A) to an RDL 312. Thesemiconductor die 310 can be coupled to the RDL 312 on an opposite sideof the RDL 312 than the removed portions of the encapsulant 314.

As illustrated in FIG. 3F (and also in FIGS. 3G-3H), the RDL 312 extendsbeyond the sides of the semiconductor die 310 which allows for the“fan-out” characteristic in a fan-out wafer-level packaging (FOWLP)process, as used in this example. The FOWLP allows for a greater numberof external input/output (I/O) and system-in-package methods as theexternal I/Os have a larger surface of RDL 312 to attach to beyond theedges of the semiconductor die 310. The process of forming thesemiconductor device can be performed using either chip-first orchip-last methods. A chip-first method includes a die being attached toa temporary or permanent material structure prior to making an RDL thatwill extend from the die to a BGA (ball grid array) interface. BGA is atype of surface-mount packaging (a chip carrier) used for integratedcircuits. BGA packages can be used to permanently mount devices such asmicroprocessors. A BGA can provide more interconnection pins that can beput on a dual in-line or flat package. In this manner, the yield loss isassociated with creating the RDL after the die is mounted, subjectingthe die to potential loss.

In a chip-last process, the RDL is created first and then the die ismounted. In this chip-last process, the RDL structure can be eitherelectrically tested or visually inspected for yield loss, therebyavoiding placing a good die on bad sites. For low I/O die, where RDL isminimal and yields are high, a chip-first process can be preferred. Fora high value die (large I/O) (as in a fan-out layout, as illustrated) achip-last process can be preferred.

FIG. 3G is an example of a subsequent step of the method of forming thesemiconductor device that can include forming an encapsulant (e.g., anEMC layer) 314-2 enclosing the semiconductor die 310 and connecting withthe previously formed encapsulant 314-1. The encapsulant 314-2 can be asecond portion of encapsulant that is formed subsequent to a firstportion of encapsulant 314-1.

FIG. 3H is an example of a subsequent step of the method of forming thesemiconductor device that can include attaching a number of interconnectstuctures 320-1, 320-2, 320-3, 320-4, 320-5, 320-6, 320-7, referred toherein as interconnect structures 320, to the RDL 312 at locations wherethe portions of the encapsulant 314-1 were removed. In this way, theinterconnect structures 320 can be attached to the RDL 312 and portionsof the encapsulant 314-1 such that the interconnect structures 320 areheld into place by the encapsulant 314-1 to cause a stronger solderjoint. The interconnect structures 320 can have stronger solder jointswithout adding underfill material to the interconnect structures 320 andthe underside of the RDL 312.

FIGS. 4A-4H are an example of a method of forming a semiconductor devicein accordance with a number of embodiments of the present disclosure.FIG. 4A is an example of an initial step of the method of forming thesemiconductor device which can include making a semiconductor die 410for coupling to a redistribution layer later in the method. FIG. 4B isan example of a subsequent step of the method of forming thesemiconductor device that can include forming a redistribution layer 412on a carrier substrate 426. The carrier substrate 426 can include aglass carrier, a silicon carrier, among other materials. FIG. 4C is anexample of a subsequent step of the method of forming the semiconductordevice that can include attaching a number of interconnect structures(e.g., solderballs) 420-1, 420-2, 420-3, 420-4, 420-5, 420-6, 420-7,referred to herein as interconnect structures 420, to the RDL 412.

FIG. 4D is an example of a subsequent step of the method of forming thesemiconductor device that can include using injection molding to form anencapsulant (e.g., an EMC layer) 414 between each of the interconnectstructures 420 and at the ends 415-1, 415-2 of the RDL 412.

FIG. 4E is an example of a subsequent step, that is alternative to thesubsequent step described in FIG. 4D, of the method of forming thesemiconductor device. The alternative step can include using compressionmolding (illustrated as compression arrows 430), as opposed to injectionmolding as described in FIG. 4D, to form the EMC layer 414 between eachof the interconnect structures 420 and at the ends 415-1, 415-2 of theRDL 412. Either of the steps illustrated in FIGS. 4D and 4E can be usedto form the encapsulant 414, as illustrated. As illustrated in FIGS. 4Dand 4E, the edge of the RDL 412 can be encased within the EMC layer 414.By encasing the edge of the RDL 412 within the encapsulant layer 414,the RDL 412 can be protected from interfacial delamination,crack-induced mechanical stress, and moisture impact. The interfacialdelamination, crack-induced mechanical stress, and/or moisture impactcan occur along the edges of the RDL 412 in the absence of (or when theRDL 412 edges are without) the encapsulant 414 at the edges 415-1, 415-2during an assembly process and/or during use.

FIG. 4F is an example of a subsequent step of the method of forming thesemiconductor device that can include removing a carrier substrate, suchas carrier substrate 426 illustrated in FIGS. 4A-4E. FIG. 4G is anexample of a subsequent step of the method of forming the semiconductordevice. FIG. 4G illustrates the RDL 412, the encapsulant 414, and theinterconnect structures 420 rotates 180 degrees. The step illustrated inFIG. 4G can include coupling a semiconductor die 410 (such assemiconductor die 410 described in FIG. 4A) to the RDL 412. Thesemiconductor die 410 can be coupled to the RDL 412 on an opposite sideof the RDL 412 than the interconnect structures 420. As illustrated inFIG. 4G, the RDL 412 extends beyond the sides of the semiconductor chip410 which allows for the “fan-out” characteristic in a fan-outwafer-level packaging (FOWLP) process, as used in this example. TheFOWLP allows for a greater number of external input/output (I/O) andsystem-in-package methods, as described further above.

FIG. 4H is an example of a subsequent step of the method of forming thesemiconductor device that can include forming an encapsulant 414-2enclosing the semiconductor die 410 and connecting with the previouslyformed encapsulant 414-1. The encapsulant 414-2 can be a second portionof encapsulant that is formed subsequent to a first portion ofencapsulant 414-1.

Although specific embodiments have been illustrated and describedherein, those of ordinary skill in the art will appreciate that anarrangement calculated to achieve the same results can be substitutedfor the specific embodiments shown. This disclosure is intended to coveradaptations or variations of various embodiments of the presentdisclosure.

It is to be understood that the above description has been made in anillustrative fashion, and not a restrictive one. Combination of theabove embodiments, and other embodiments not specifically describedherein will be apparent to those of skill in the art upon reviewing theabove description. The scope of the various embodiments of the presentdisclosure includes other applications in which the above structures andmethods are used. Therefore, the scope of various embodiments of thepresent disclosure should be determined with reference to the appendedclaims, along with the full range of equivalents to which such claimsare entitled.

In the foregoing Detailed Description, various features are groupedtogether in a single embodiment for the purpose of streamlining thedisclosure. This method of disclosure is not to be interpreted asreflecting an intention that the disclosed embodiments of the presentdisclosure have to use more features than are expressly recited in eachclaim.

Rather, as the following claims reflect, inventive subject matter liesin less than all features of a single disclosed embodiment. Thus, thefollowing claims are hereby incorporated into the Detailed Description,with each claim standing on its own as a separate embodiment.

1. A semiconductor device, comprising: a semiconductor die comprisingopposing sides; a redistribution layer (RDL) formed on a first surfaceof the semiconductor die and coupled to a printed circuit board (PCB),wherein: opposing sides of the RDL extend completely beyond the opposingsides of the semiconductor die; and there is not a semiconductor diethat extends beyond the opposing sides of the RDL; an encapsulant thatencloses a second surface and side surfaces of the semiconductor die andside portions of the RDL.
 2. The semiconductor device of claim 1,wherein the encapsulant encloses a portion of the RDL that is not incontact with the semiconductor die.
 3. The semiconductor device of claim1, wherein the RDL extends beyond an edge of the semiconductor die. 4.The semiconductor device of claim 1, wherein interconnect structures areattached to a side of the RDL opposite the semiconductor die.
 5. Thesemiconductor device of claim 4, wherein the encapsulant enclosesportions of the RDL between the interconnect structures.
 6. Asemiconductor device, comprising: a semiconductor die comprisingopposing sides; a redistribution layer (RDL) formed on a first surfaceof the semiconductor die and coupled to a printed circuit board (PCB),wherein: the RDL extends completely beyond the opposing sides of thesemiconductor die; and there is only encapsulant between an edge of theRDL that extends completely beyond the opposing sides and a top of theencapsulant and the semiconductor die is between the RDL and the top ofthe encapsulant; interconnect structures formed on a second surface ofthe RDL; an encapsulant that encloses a second surface and side surfacesof the semiconductor die and portions of the RDL between theinterconnect structures.
 7. The semiconductor device of claim 6, whereinthe RDL extends beyond an edge of one of the opposing sides of thesemiconductor die.
 8. The semiconductor device of claim 6, wherein theencapsulant encloses side portions of the RDL.
 9. The semiconductordevice of claim 6, wherein the interconnect structures are not coveredby underfill material.
 10. The semiconductor device of claim 6, whereinthe encapsulant that encloses the portions of the RDL between theinterconnect structures are configured to hold the interconnectstructures in place and against the RDL.
 11. A method of forming asemiconductor device, comprising: forming a redistribution layer (RDL)on a carrier substrate; forming a first encapsulant on the RDL; removinga number of portions out of the first encapsulant; detaching the carriersubstrate; attaching a semiconductor die to the RDL in place of thedetached carrier substrate, wherein: the semiconductor die comprisesopposing sides and the RDL extends completely beyond the opposing sidesof the semiconductor die; and there is not a semiconductor die thatextends beyond opposing sides of the RDL; forming a second encapsulantthat encloses the semiconductor die and portions of the RDL facingtoward but not in contact with the semiconductor die; and attaching anumber of interconnect structures into each of the number of portionsremoved from the first encapsulant.
 12. The method of claim 11, whereinforming the first encapsulant comprises forming the first encapsulant toenclose side portions of the RDL.
 13. The method of claim 12, whereinthe second encapsulant is formed to connect, at the side portions of theRDL, to the first encapsulant. 14-16. (canceled)
 17. A method forforming a semiconductor device, comprising: forming a redistributionlayer (RDL) on a carrier substrate; attaching a number of interconnectstructures onto a surface of the RDL opposite the carrier substrate;molding a first encapsulant onto the RDL between each of the number ofinterconnect structures; detaching the carrier substrate; attaching asemiconductor die to the RDL in place of the detached carrier substrate,wherein: semiconductor die comprises opposing sides; the RDL completelyextends beyond the opposing sides of the semiconductor die; there isonly encapsulant between an edge of the RDL that extends completelybeyond the opposing sides of the semiconductor die and a top of theencapsulant and the semiconductor die is between the RDL and the top ofthe encapsulant; and the RDL is between the semiconductor die and aprinted circuit board; forming a second encapsulant that encloses thesemiconductor die.
 18. The method of claim 17, wherein molding the firstencapsulant onto the RDL layer includes using an injection moldingprocess.
 19. The method of claim 17, wherein molding of the firstencapsulant onto the RDL layer includes using a compression moldingprocess.
 20. (canceled)
 21. The method of claim 17, wherein the numberof interconnect structures are attached beyond edges of thesemiconductor die associated with the opposing sides of thesemiconductor die.
 22. The method of claim 1, wherein: there is onlyencapsulant between the edge of the RDL that extends completely beyondthe opposing sides and a top of the encapsulant; and the semiconductordie is between the RDL and the top of the encapsulant.
 23. The method ofclaim 1, wherein the RDL is between the semiconductor die and the PCB.24. The method of claim 6, wherein opposing sides of the RDL areextending completely beyond the opposing sides of the semiconductor dieand there is not a semiconductor die that extends beyond the opposingsides of the RDL.
 25. The method of claim 6, wherein the RDL is betweenthe semiconductor die and the PCB.